One or more embodiments relate to a nonvolatile memory device with an improved structure and a program or verification method using the same.
Recently, there is an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and do not require the refresh function of rewriting data at specific periods.
A nonvolatile memory cell enables electrical program/erase operations and performs the program and erase operations through a threshold voltage that varies when electrons are migrated by a strong electric field applied to a thin oxide layer.
The nonvolatile memory device typically includes a memory cell array in which cells for storing data are arranged in a matrix form and a page buffer for writing data into specific cells of the memory cell array or reading data stored in specific cells thereof. The page buffer includes a bit line select unit configured to selectively connect any one of an even bit line and an odd bit line to a sensing node, a sensing node precharge unit configured to apply a power supply voltage of a high level to the sensing node, a data latch unit configured to temporarily store data to be programmed into cells or to temporarily store data read from cells, a data setting unit configured to input data to be stored in the data latch unit, a sensing node sensing unit configured to apply a ground voltage to a specific node of the data latch unit depending on the level of the sensing node, a data transfer unit configured to apply data, stored in the data latch unit, to the sensing node, and a bit line sensing unit configured to selectively connect the sensing node and a bit line selected by the bit line select unit.
The nonvolatile memory device is becoming highly integrated as a technology develops. There has been a trend where the critical dimension (CD) between bit lines connected to respective memory cell strings has been decreasing. Accordingly, more current may be consumed when the bit lines of a nonvolatile memory device using a boosting scheme are discharged because of increased parasitic capacitance between the bit lines.
In particular, in the bit line sensing unit configured to connect the sensing node and the bit line through a bit line sensing signal, the voltage level of the bit line sensing signal may abruptly change from a low level to a high level, so a current value flowing through the bit line suddenly increases. Accordingly, it may be desirable to minimize the occurrence of the peak current resulting from the bit line sensing signal.